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Bengtsson , Olof
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Publications (10 of 16) Show all publications
Bengtsson, O., Vestling, L. & Olsson, J. (2009). A Computational Load-Pull Method with Harmonic Loading for High-Efficiency Investigations. Solid-State Electronics, 53(1), 86-94
Open this publication in new window or tab >>A Computational Load-Pull Method with Harmonic Loading for High-Efficiency Investigations
2009 (English)In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 53, no 1, p. 86-94Article in journal (Refereed) Published
Abstract [en]

In this paper a method for TCAD evaluation of RF-power transistors in highefficiency operation using harmonic loading is presented. The method is based on large signal timedomain

computational load-pull. Active loads are used in the harmonic load-pull for simulation time reduction. With the method device performance under different harmonic load impedance can

be investigated at an early stage in the design process. Alternative designs can be compared and the mechanisms affecting device efficiency in class-F can be studied at chip level. For method validation a case study is made on an LDMOS transistor. The transistor is load-pulled in class-AB and then optimized for efficiency at 2f0 and 3f0 using a novel approach with passive fundamental load and active harmonic loads. A swept simulation is conducted using passive fundamental and

harmonic loads. Waveforms in compression are analyzed and the mechanisms creating the increased efficiency for in class-F are indentified by a comparative study of class-AB. Class-F harmonic termination is shown to give a 17 % overall reduction of dissipated power and a 9 % increase in output power. The expected efficiency increase is about 3-10 % in the compression

region depending on level of compression.

Place, publisher, year, edition, pages
Elsevier, 2009
Keywords
Load-Pull, RF-Power, Power amplifiers, TCAD
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:hig:diva-2234 (URN)10.1016/j.sse.2008.10.005 (DOI)000262552200015 ()2-s2.0-57449104665 (Scopus ID)
Available from: 2008-10-13 Created: 2008-10-13 Last updated: 2018-03-13Bibliographically approved
Ramachandran , P., Bengtsson , O. & Beckman, C. (2009). Impedance determination of terminal power amplifiers for optimal antenna matching using load-pull method. In: 2009 IEEE International Workshop on Antenna Technology: iWAT2009 : "Small Antennas and Novel Metamaterials". Santa Monica, California
Open this publication in new window or tab >>Impedance determination of terminal power amplifiers for optimal antenna matching using load-pull method
2009 (English)In: 2009 IEEE International Workshop on Antenna Technology: iWAT2009 : "Small Antennas and Novel Metamaterials", Santa Monica, California, 2009Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we present a single tuner based load-pull method for characterization of optimal antenna load impedance in mobile terminals. In the proposed load-pull set-up the mobile terminal itself is used as a source. The presented method can provide valuable data for antenna design since it determines the optimal impedance at the antenna connector/pad taken into account the full output circuitry of the mobile terminal. It reveals the modification of the power amplifier, PA, output impedance caused by the presence of saw filter, antenna switch, and transmission line possibly present between the PA and the antenna. With the presented method it is not only possible to characterize the optimum antenna impedance to present to the terminal in different bands and channels but also to reveal the impedance miss-match sensitivity for each channel.

Place, publisher, year, edition, pages
Santa Monica, California: , 2009
Identifiers
urn:nbn:se:hig:diva-4039 (URN)
Note
2009 IEEE International Workshop on Antenna Technology: iWAT2009 : "Small Antennas and Novel Metamaterials", March 2–4, 2009, Santa Monica, California Available from: 2009-04-29 Created: 2009-03-31 Last updated: 2018-03-13Bibliographically approved
Vestling, L., Bengtsson, O., Eklund, K.-H. & Olsson, J. (2009). Increased efficiency in RF-power SOI-LDMOS transistors. In: EUROSOI 2009 - Conference Proceedings: Fifth Workshop of the Thematic Network on Silicon-On-Insulator, Technology, Devices and Circuits (pp. 117-118).
Open this publication in new window or tab >>Increased efficiency in RF-power SOI-LDMOS transistors
2009 (English)In: EUROSOI 2009 - Conference Proceedings: Fifth Workshop of the Thematic Network on Silicon-On-Insulator, Technology, Devices and Circuits, 2009, p. 117-118Conference paper, Published paper (Refereed)
Abstract [en]

The effect of substrate resistivity on efficiency in high-power operation of high-frequency SOI-LDMOS transistors is for the first time investigated using computational load-pull simulations. Identical SOI-LDMOS transistors have been studied on different substrate resistivities. Their highpower performance has been compared to previous investigations concerning the off-state ROUT to high-efficiency relation. It is shown that albeit high off-state ROUT is a good indication it may not always be sufficient for high efficiency operation. The bias and frequency dependency of the coupling through the substrate makes a more detailed on-state analysis necessary. It is shown that very low resistivity and high resistivity SOI-substrates both result in high efficiency at the studied frequency and bias-point. It is also shown thata normally doped, medium resistivity, substrate results in significantly lower efficiency.

 

 

 

 

 

 

 

Keywords
SOI, Load-Pull, Power Amplifier
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:hig:diva-3690 (URN)
Available from: 2009-02-04 Created: 2009-02-04 Last updated: 2018-03-13Bibliographically approved
Bengtsson, O., Vestling, L. & Olsson, J. (2009). Investigation of SOI-LDMOS for RF-Power Applications Using Computational Load Pull. IEEE Transactions on Electron Devices, 56(3), 505-511
Open this publication in new window or tab >>Investigation of SOI-LDMOS for RF-Power Applications Using Computational Load Pull
2009 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 56, no 3, p. 505-511Article in journal (Refereed) Published
Abstract [en]

Small-signal and computational load-pull simulations are used to investigate the effect of substrate resistivity on efficiency in high-power operation of high-frequency silicon-on insulator-LDMOS transistors. Identical transistors are studied on substrates with different resistivities. Using computational load pull, their high-power performance is evaluated. The results are compared to previous investigations, relating the OFF-state out put resistance to high-efficiency operation. From the large-signal simulation, an output circuit model based on a load-line match is extracted with parameters traceable from small-signal simu lations. It is shown that, albeit high OFF-state output resistance is a good indication, it is not sufficient for high efficiency in a high-power operation. The bias and frequency dependence of the coupling through the substrate makes a more detailed ON-state analysis necessary. It is shown that very low resistivity and high resistivity SOI substrates both result in a high efficiency at the studied frequency and bias point. It is also shown that a normally doped medium-resistivity substrate results in a significantly lower efficiency.

Place, publisher, year, edition, pages
IEEE, 2009
Keywords
LDMOS, RF power, silicon-on-insulator (SOI)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:hig:diva-3692 (URN)10.1109/TED.2008.2011848 (DOI)000264019300019 ()2-s2.0-62749086718 (Scopus ID)
Available from: 2009-02-04 Created: 2009-02-04 Last updated: 2018-03-13Bibliographically approved
diva2:118309
Open this publication in new window or tab >>A Computational Load-Pull Investigation of Harmonic Loading effects on AM-PM conversion
2008 (English)In: GigaHertz Symposium 2008: Abstract Book, 2008, p. 83-83Conference paper, Published paper (Other academic)
Abstract [en]

In this work computational harmonic load-pull have been used to study the effect of harmonic loading on AM-PM conversion for an RF-Power LDMOS transistor. It is found that especially the load impedance seen at the 2nd harmonic has a large impact (up to 2° or 15% difference) on the phase distortion at P1dB in this investigation conducted at chip level.

Series
Technical report, ISSN 1642-0769 ; MC2-125
Keywords
Load-Pull, TCAD
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:hig:diva-1647 (URN)
Available from: 2008-04-02 Created: 2008-04-02 Last updated: 2018-03-13Bibliographically approved
Bengtsson, O., Vestling, L. & Olsson, J. (2008). A Computational Load-Pull Method for TCAD Optimization of RF-Power Transistors in Bias-Modulation Applications. In: 2008 European Microwave Integrated Circuits Conference (EuMIC): . Paper presented at 3rd European Microwave Integrated Circuits Conference (EuMIC), Amsterdam, 27-28 July 2008 (pp. 222-225).
Open this publication in new window or tab >>A Computational Load-Pull Method for TCAD Optimization of RF-Power Transistors in Bias-Modulation Applications
2008 (English)In: 2008 European Microwave Integrated Circuits Conference (EuMIC), 2008, p. 222-225Conference paper, Published paper (Refereed)
Abstract [en]

Abstract— In this paper a method for TCAD evaluation of RF-Power transistors for high-efficiency operation using drain bias-modulation is presented. The method is based on large signal time-domain transient computational load-pull. With the method, intrinsic device parasitics and mechanisms affecting device efficiency under drain bias modulation can be investigated and optimized for the application making it very useful for RFIC design. A case study has been done on a CMOS compatible LDMOS. For verification under dynamic operation two-tone signals with varying envelope has been simulated. The results show a possible 15% increase in the efficiency of a modulated signal for the studied device at the expense of increased phase distortion observable also in the time-domain waveforms generated. Since the method is based on TCAD it is also useful in the investigation of e.g. dynamic breakdown during high envelope under bias-modulation operation.

National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:hig:diva-1947 (URN)10.1109/EMICC.2008.4772269 (DOI)000268721400057 ()978-2-87487-007-1 (ISBN)
Conference
3rd European Microwave Integrated Circuits Conference (EuMIC), Amsterdam, 27-28 July 2008
Available from: 2008-06-09 Created: 2008-06-09 Last updated: 2018-03-13Bibliographically approved
Bengtsson, O. (2008). Design and Characterization of RF-Power LDMOS Transistors. (Doctoral dissertation). Uppsala: Uppsala Universitet
Open this publication in new window or tab >>Design and Characterization of RF-Power LDMOS Transistors
2008 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In mobile communication new applications like wireless internet and mobile video have increased the demand of data-rates. Therefore, new more wideband systems are being implemented. Power amplifiers in the base-stations that simultaneously handle these wideband signals for many terminals (handhelds) need to be highly linear with a considerable band-width.

In the past decade LDMOS has been the dominating technology for use in these RF-power amplifiers. In this work LDMOS transistors possible to fabricate in a normal CMOS process have been optimized and analyzed for RF-power applications. Their non-linear behavior has been explored using load-pull measurements. The mechanisms of the non-linear input capacitance have been analyzed using 2D TCAD simulations. The investigation shows that the input capacitance is a large contributor to phase distortion in the transistor.

Computational load-pull TCAD methods have been developed for analysis of RF-power devices in high-efficiency operation. Methods have been developed for class-F with harmonic loading and for bias-modulation. Load-pull measurements with drain-bias modulation in a novel measurement setup have also been conducted. The investigation shows that the combination of computational load-pull of physical transistor structures and direct measurement evaluation with modified load-pull is a viable alternative for future design of RF-power devices. Simulations and measurements on the designed LDMOS shows a 10 to 15 % increase in drain efficiency in mid-power range both in simulations and measurements. The computational load-pull method has also been used to investigate the power capability of LDMOS transistors on SOI. This study indicates that either a low-resistivity or high-resistivity substrate should be used in manufacturing of RF-power LDMOS transistors on SOI to achieve optimum efficiency. Based on a proper substrate selection these devices exhibit a 10 % higher drain-efficiency mainly due to lower dissipated power in the devices.

Place, publisher, year, edition, pages
Uppsala: Uppsala Universitet, 2008. p. 160
Keywords
Power Amplifiers, LDMOS transistors, RF-power, IMD, Technology CAD, Load-Pull
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:hig:diva-2233 (URN)978-91-554-7269-6 (ISBN)
Public defence
(English)
Available from: 2008-10-08 Created: 2008-10-08 Last updated: 2018-03-13Bibliographically approved
Vestling, L., Bengtsson, O. & Olsson, J. (2008). High Efficiency using Optimized SOI-Substrates. In: Gigahertz Symposium 2008: Abstract Book (pp. 94-94). Göteborg: Chalmers
Open this publication in new window or tab >>High Efficiency using Optimized SOI-Substrates
2008 (English)In: Gigahertz Symposium 2008: Abstract Book, Göteborg: Chalmers , 2008, p. 94-94Conference paper, Published paper (Other academic)
Abstract [en]

Abstract—The effect of the substrate resistivity on

the efficiency for high-frequency SOI-LDMOS transistors

is studied using computational load-pull simulations.

It is shown that very low resistivity and

high resistivity SOI-substrates both result in high

efficiency. It is also shown that a normally doped,

medium resistivity, substrate results in significantly

lower efficiency.

Place, publisher, year, edition, pages
Göteborg: Chalmers, 2008
Series
Technical report, ISSN 1642-0769 ; MC2-125
Keywords
SOI, Efficiency, LDMOS
Identifiers
urn:nbn:se:hig:diva-1662 (URN)
Available from: 2008-04-28 Created: 2008-04-28 Last updated: 2018-03-13Bibliographically approved
Bengtsson, O., Vestling, L. & Olsson, J. (2008). Investigation of the Nonlinear Input Capacitance in LDMOS Transistors and its Contribution to IMD and Phase Distortion. Solid-State Electronics, 52(7), 1024-1031
Open this publication in new window or tab >>Investigation of the Nonlinear Input Capacitance in LDMOS Transistors and its Contribution to IMD and Phase Distortion
2008 (English)In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 52, no 7, p. 1024-1031Article in journal (Refereed) Published
Abstract [en]

In this paper the mechanisms causing the capacitive, reactive non-linearities in a lateral double diffused MOS, LDMOS, transistor are investigated. The non-linear input capacitance under load-line power match is extracted and analyzed. Computational TCAD load-pull is used to analyze the effect of non-linear capacitance on two-tone intermodulation distortion and AM–PM conversion in class-A operation. High-frequency measurements have been made to verify the use of 2D numerical device simulations for the analysis. It is found that the input capacitance, Cgg, of the LDMOS transistor working under power match conditions is a strongly non-linear function of gate voltage Vg but with an almost linear initial increase in Cgg. The voltage dependence of Cgg is found to mainly affect higher order IMD products in class-A operation. Transient simulations however show that Cgg seriously contributes to the onset of AM–PM conversion well below the 1 dB compression point.

Keywords
LDMOS Transistors, RF-Power, Power Amplifiers, IMD
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:hig:diva-1939 (URN)10.1016/j.sse.2008.03.001 (DOI)000257972500006 ()2-s2.0-44749088400 (Scopus ID)
Available from: 2008-06-09 Created: 2008-06-09 Last updated: 2018-03-13Bibliographically approved
Castillo, P., San-Roman, E. & Bengtsson, O. (2007). On the design of a planar, harmonic, triplex-filter for 3G, load-pull measurement applications. In: RFMTC-07.
Open this publication in new window or tab >>On the design of a planar, harmonic, triplex-filter for 3G, load-pull measurement applications
2007 (English)In: RFMTC-07, 2007Conference paper, Published paper (Other (popular science, discussion, etc.))
Abstract [en]

This paper describes the design of a planar harmonic triplex-filter for 3G load-pull measurement applications. The designs are based on planar 2D field simulations on individual and combined filters of different structures like stepped impedance, coupled lines and ring resonators. Triplex-filters of different combinations on Teflon substrate and mixed substrates for loss reduction were simulated, fabricated and evaluated in this work. It is found that using lithographic process on Teflon with SMA endlaunchers a filter with 0.44 dB f0 insertion loss, IL, and 50 dB isolation can be achieved. On the low loss substrate the mechanical design process limits the results to about 1.0 dB IL. Low loss launchers and substrate interconnects are suggested and 3D simulations performed for the mixed design.

Keywords
Triplex Filter, Load-Pull
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:hig:diva-2678 (URN)
Note
Conference on RF Measurement Technology, for State of The Art Production and Design, Sep 11-12, 2007, GävleAvailable from: 2007-10-05 Created: 2007-10-05 Last updated: 2018-03-13Bibliographically approved
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