In this paper a method for TCAD evaluation of RF-power transistors in highefficiency operation using harmonic loading is presented. The method is based on large signal timedomain

computational load-pull. Active loads are used in the harmonic load-pull for simulation time reduction. With the method device performance under different harmonic load impedance can

be investigated at an early stage in the design process. Alternative designs can be compared and the mechanisms affecting device efficiency in class-F can be studied at chip level. For method validation a case study is made on an LDMOS transistor. The transistor is load-pulled in class-AB and then optimized for efficiency at 2f0 and 3f0 using a novel approach with passive fundamental load and active harmonic loads. A swept simulation is conducted using passive fundamental and

harmonic loads. Waveforms in compression are analyzed and the mechanisms creating the increased efficiency for in class-F are indentified by a comparative study of class-AB. Class-F harmonic termination is shown to give a 17 % overall reduction of dissipated power and a 9 % increase in output power. The expected efficiency increase is about 3-10 % in the compression

region depending on level of compression.

In this paper we present a single tuner based load-pull method for characterization of optimal antenna load impedance in mobile terminals. In the proposed load-pull set-up the mobile terminal itself is used as a source. The presented method can provide valuable data for antenna design since it determines the optimal impedance at the antenna connector/pad taken into account the full output circuitry of the mobile terminal. It reveals the modification of the power amplifier, PA, output impedance caused by the presence of saw filter, antenna switch, and transmission line possibly present between the PA and the antenna. With the presented method it is not only possible to characterize the optimum antenna impedance to present to the terminal in different bands and channels but also to reveal the impedance miss-match sensitivity for each channel.

The effect of substrate resistivity on efficiency in high-power operation of high-frequency SOI-LDMOS transistors is for the first time investigated using computational load-pull simulations. Identical SOI-LDMOS transistors have been studied on different substrate resistivities. Their highpower performance has been compared to previous investigations concerning the off-state ROUT to high-efficiency relation. It is shown that albeit high off-state ROUT is a good indication it may not always be sufficient for high efficiency operation. The bias and frequency dependency of the coupling through the substrate makes a more detailed on-state analysis necessary. It is shown that very low resistivity and high resistivity SOI-substrates both result in high efficiency at the studied frequency and bias-point. It is also shown thata normally doped, medium resistivity, substrate results in significantly lower efficiency.

Small-signal and computational load-pull simulations are used to investigate the effect of substrate resistivity on efficiency in high-power operation of high-frequency silicon-on insulator-LDMOS transistors. Identical transistors are studied on substrates with different resistivities. Using computational load pull, their high-power performance is evaluated. The results are compared to previous investigations, relating the OFF-state out put resistance to high-efficiency operation. From the large-signal simulation, an output circuit model based on a load-line match is extracted with parameters traceable from small-signal simu lations. It is shown that, albeit high OFF-state output resistance is a good indication, it is not sufficient for high efficiency in a high-power operation. The bias and frequency dependence of the coupling through the substrate makes a more detailed ON-state analysis necessary. It is shown that very low resistivity and high resistivity SOI substrates both result in a high efficiency at the studied frequency and bias point. It is also shown that a normally doped medium-resistivity substrate results in a significantly lower efficiency.

In this work computational harmonic load-pull have been used to study the effect of harmonic loading on AM-PM conversion for an RF-Power LDMOS transistor. It is found that especially the load impedance seen at the 2nd harmonic has a large impact (up to 2° or 15% difference) on the phase distortion at P1dB in this investigation conducted at chip level.

Abstract— In this paper a method for TCAD evaluation of RF-Power transistors for high-efficiency operation using drain bias-modulation is presented. The method is based on large signal time-domain transient computational load-pull. With the method, intrinsic device parasitics and mechanisms affecting device efficiency under drain bias modulation can be investigated and optimized for the application making it very useful for RFIC design. A case study has been done on a CMOS compatible LDMOS. For verification under dynamic operation two-tone signals with varying envelope has been simulated. The results show a possible 15% increase in the efficiency of a modulated signal for the studied device at the expense of increased phase distortion observable also in the time-domain waveforms generated. Since the method is based on TCAD it is also useful in the investigation of e.g. dynamic breakdown during high envelope under bias-modulation operation.

In mobile communication new applications like wireless internet and mobile video have increased the demand of data-rates. Therefore, new more wideband systems are being implemented. Power amplifiers in the base-stations that simultaneously handle these wideband signals for many terminals (handhelds) need to be highly linear with a considerable band-width.

In the past decade LDMOS has been the dominating technology for use in these RF-power amplifiers. In this work LDMOS transistors possible to fabricate in a normal CMOS process have been optimized and analyzed for RF-power applications. Their non-linear behavior has been explored using load-pull measurements. The mechanisms of the non-linear input capacitance have been analyzed using 2D TCAD simulations. The investigation shows that the input capacitance is a large contributor to phase distortion in the transistor.

Computational load-pull TCAD methods have been developed for analysis of RF-power devices in high-efficiency operation. Methods have been developed for class-F with harmonic loading and for bias-modulation. Load-pull measurements with drain-bias modulation in a novel measurement setup have also been conducted. The investigation shows that the combination of computational load-pull of physical transistor structures and direct measurement evaluation with modified load-pull is a viable alternative for future design of RF-power devices. Simulations and measurements on the designed LDMOS shows a 10 to 15 % increase in drain efficiency in mid-power range both in simulations and measurements. The computational load-pull method has also been used to investigate the power capability of LDMOS transistors on SOI. This study indicates that either a low-resistivity or high-resistivity substrate should be used in manufacturing of RF-power LDMOS transistors on SOI to achieve optimum efficiency. Based on a proper substrate selection these devices exhibit a 10 % higher drain-efficiency mainly due to lower dissipated power in the devices.

Abstract—The effect of the substrate resistivity on

the efficiency for high-frequency SOI-LDMOS transistors

is studied using computational load-pull simulations.

It is shown that very low resistivity and

high resistivity SOI-substrates both result in high

efficiency. It is also shown that a normally doped,

medium resistivity, substrate results in significantly

lower efficiency.

In this paper the mechanisms causing the capacitive, reactive non-linearities in a lateral double diffused MOS, LDMOS, transistor are investigated. The non-linear input capacitance under load-line power match is extracted and analyzed. Computational TCAD load-pull is used to analyze the effect of non-linear capacitance on two-tone intermodulation distortion and AM–PM conversion in class-A operation. High-frequency measurements have been made to verify the use of 2D numerical device simulations for the analysis. It is found that the input capacitance, Cgg, of the LDMOS transistor working under power match conditions is a strongly non-linear function of gate voltage Vg but with an almost linear initial increase in Cgg. The voltage dependence of Cgg is found to mainly affect higher order IMD products in class-A operation. Transient simulations however show that Cgg seriously contributes to the onset of AM–PM conversion well below the 1 dB compression point.

This paper describes the design of a planar harmonic triplex-filter for 3G load-pull measurement applications. The designs are based on planar 2D field simulations on individual and combined filters of different structures like stepped impedance, coupled lines and ring resonators. Triplex-filters of different combinations on Teflon substrate and mixed substrates for loss reduction were simulated, fabricated and evaluated in this work. It is found that using lithographic process on Teflon with SMA endlaunchers a filter with 0.44 dB f0 insertion loss, IL, and 50 dB isolation can be achieved. On the low loss substrate the mechanical design process limits the results to about 1.0 dB IL. Low loss launchers and substrate interconnects are suggested and 3D simulations performed for the mixed design.