The effect of substrate resistivity on efficiency in high-power operation of high-frequency SOI-LDMOS transistors is for the first time investigated using computational load-pull simulations. Identical SOI-LDMOS transistors have been studied on different substrate resistivities. Their highpower performance has been compared to previous investigations concerning the off-state ROUT to high-efficiency relation. It is shown that albeit high off-state ROUT is a good indication it may not always be sufficient for high efficiency operation. The bias and frequency dependency of the coupling through the substrate makes a more detailed on-state analysis necessary. It is shown that very low resistivity and high resistivity SOI-substrates both result in high efficiency at the studied frequency and bias-point. It is also shown thata normally doped, medium resistivity, substrate results in significantly lower efficiency.