In this paper a method for TCAD evaluation of RF-power transistors in highefficiency operation using harmonic loading is presented. The method is based on large signal timedomain

computational load-pull. Active loads are used in the harmonic load-pull for simulation time reduction. With the method device performance under different harmonic load impedance can

be investigated at an early stage in the design process. Alternative designs can be compared and the mechanisms affecting device efficiency in class-F can be studied at chip level. For method validation a case study is made on an LDMOS transistor. The transistor is load-pulled in class-AB and then optimized for efficiency at 2f0 and 3f0 using a novel approach with passive fundamental load and active harmonic loads. A swept simulation is conducted using passive fundamental and

harmonic loads. Waveforms in compression are analyzed and the mechanisms creating the increased efficiency for in class-F are indentified by a comparative study of class-AB. Class-F harmonic termination is shown to give a 17 % overall reduction of dissipated power and a 9 % increase in output power. The expected efficiency increase is about 3-10 % in the compression

region depending on level of compression.