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Design of a Digital Down Converter for LTE in an FPGA
University of Gävle, Faculty of Engineering and Sustainable Development.
2010 (English)Independent thesis Basic level (degree of Bachelor), 10 credits / 15 HE creditsStudent thesis
Abstract [en]

In thesis a Digital Down Converter (DDC) for Long Term Evolution (LTE) signals is designed. The DDC shall be implemented in hardware in a Field Programmable Gate Array (FPGA). For an FPGA the desired operating speed is high. The purpose of this thesis is therefore to determine if it is possible to design such a system.

 The proposed DDC design consists of an efficient quadrature demodulator and a data rate decimation system. The decimation system consists of a Cascaded Integrator Comb (CIC) filter and a compensating Finite Impulse Response (FIR) filer. It is shown how the CIC and FIR filter can be made parallel in order to increase the data rate while still maintaining the clock speed.

This thesis shows that it is possible to design an FPGA based DDC for LTE signals with a decimation factor of 13, running at 399.36 MHz. The estimated performance increase of FPGA based design compared to the software based design is 319 times. Since floating-point numbers is inefficient to implement in hardware, thesis uses integer filter coefficients. This introduced gain in the system. This shows that fixed-point filter coefficients is to prefer.

Abstract [sv]

I den här uppsatsen utvecklas en digital nerkonverterare (DDC) för signaler inom Long Term Evolution (LTE). DDC:n skall implementeras i hårdvara i en Field Programmable Gate Array (FPGA). Den önskade datahastigheten är hög för en FPGA. Därför är syftet med denna uppsatts att undersöka om det är möjligt att implementera ett sådant system i en FPGA.

Den framtagna designen av en DDC består av en effektiv I/Q-demodulator och ett datahastighetsdecimeringssystem. Systemet för att minska datahastigheten består av ett Cascaded Integrator Comb-filter (CIC) och ett kompenserande Finite Impulse Response-filter (FIR). Det visas hur CIC- och FIR-filter kan parallelliseras för att öka datahastigheten medan klockhastigheten bibehålls.

Det visas att det är möjligt att designa en FPGA-baserad DDC för LTE-signeler, med en decimeringsfactor på 13, som kör med en hastighet på 399.36 MHz. Den uppskattade prestandaökningen för denna FPGA-baserade lösning i jämförelse med mjukvarubaserad design är 319 gånger. I den här uppsatsen användes heltalsfilterkoefficienter eftersom flyttal inte kan implementeras effektivt i hårdvara. Detta skapade dock en oönskad förstärkning i det totala systemet. Därför är så kallade fixpunktsdecimaltal att föredra.

Place, publisher, year, edition, pages
2010. , p. 33
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:hig:diva-6879Archive number: TEX100407OAI: oai:DiVA.org:hig-6879DiVA, id: diva2:323854
Uppsok
Technology
Supervisors
Examiners
Available from: 2010-08-19 Created: 2010-06-12 Last updated: 2010-08-19Bibliographically approved

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CiteExportLink to record
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