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  • 1.
    Bengtsson, Olof
    et al.
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik.
    Vestling, Lars
    The Ångström Laboratory, Solid State Electronics, Uppsala University, Uppsala, Sweden.
    Olsson, Jörgen
    The Ångström Laboratory, Solid State Electronics, Uppsala University, Uppsala, Sweden.
    A Computational Load-Pull Method with Harmonic Loading for High-Efficiency Investigations2009In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 53, no 1, p. 86-94Article in journal (Refereed)
    Abstract [en]

    In this paper a method for TCAD evaluation of RF-power transistors in highefficiency operation using harmonic loading is presented. The method is based on large signal timedomain

    computational load-pull. Active loads are used in the harmonic load-pull for simulation time reduction. With the method device performance under different harmonic load impedance can

    be investigated at an early stage in the design process. Alternative designs can be compared and the mechanisms affecting device efficiency in class-F can be studied at chip level. For method validation a case study is made on an LDMOS transistor. The transistor is load-pulled in class-AB and then optimized for efficiency at 2f0 and 3f0 using a novel approach with passive fundamental load and active harmonic loads. A swept simulation is conducted using passive fundamental and

    harmonic loads. Waveforms in compression are analyzed and the mechanisms creating the increased efficiency for in class-F are indentified by a comparative study of class-AB. Class-F harmonic termination is shown to give a 17 % overall reduction of dissipated power and a 9 % increase in output power. The expected efficiency increase is about 3-10 % in the compression

    region depending on level of compression.

  • 2.
    Bengtsson, Olof
    et al.
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik.
    Vestling, Lars
    The Ångström Laboratory, Solid State Electronics, Uppsala University, Uppsala, Sweden.
    Olsson, Jörgen
    The Ångström Laboratory, Solid State Electronics, Uppsala University, Uppsala, Sweden.
    Investigation of the Nonlinear Input Capacitance in LDMOS Transistors and its Contribution to IMD and Phase Distortion2008In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 52, no 7, p. 1024-1031Article in journal (Refereed)
    Abstract [en]

    In this paper the mechanisms causing the capacitive, reactive non-linearities in a lateral double diffused MOS, LDMOS, transistor are investigated. The non-linear input capacitance under load-line power match is extracted and analyzed. Computational TCAD load-pull is used to analyze the effect of non-linear capacitance on two-tone intermodulation distortion and AM–PM conversion in class-A operation. High-frequency measurements have been made to verify the use of 2D numerical device simulations for the analysis. It is found that the input capacitance, Cgg, of the LDMOS transistor working under power match conditions is a strongly non-linear function of gate voltage Vg but with an almost linear initial increase in Cgg. The voltage dependence of Cgg is found to mainly affect higher order IMD products in class-A operation. Transient simulations however show that Cgg seriously contributes to the onset of AM–PM conversion well below the 1 dB compression point.

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