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  • 1.
    Bengtsson, Olof
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik.
    Design and Characterization of RF-Power LDMOS Transistors2008Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    In mobile communication new applications like wireless internet and mobile video have increased the demand of data-rates. Therefore, new more wideband systems are being implemented. Power amplifiers in the base-stations that simultaneously handle these wideband signals for many terminals (handhelds) need to be highly linear with a considerable band-width.

    In the past decade LDMOS has been the dominating technology for use in these RF-power amplifiers. In this work LDMOS transistors possible to fabricate in a normal CMOS process have been optimized and analyzed for RF-power applications. Their non-linear behavior has been explored using load-pull measurements. The mechanisms of the non-linear input capacitance have been analyzed using 2D TCAD simulations. The investigation shows that the input capacitance is a large contributor to phase distortion in the transistor.

    Computational load-pull TCAD methods have been developed for analysis of RF-power devices in high-efficiency operation. Methods have been developed for class-F with harmonic loading and for bias-modulation. Load-pull measurements with drain-bias modulation in a novel measurement setup have also been conducted. The investigation shows that the combination of computational load-pull of physical transistor structures and direct measurement evaluation with modified load-pull is a viable alternative for future design of RF-power devices. Simulations and measurements on the designed LDMOS shows a 10 to 15 % increase in drain efficiency in mid-power range both in simulations and measurements. The computational load-pull method has also been used to investigate the power capability of LDMOS transistors on SOI. This study indicates that either a low-resistivity or high-resistivity substrate should be used in manufacturing of RF-power LDMOS transistors on SOI to achieve optimum efficiency. Based on a proper substrate selection these devices exhibit a 10 % higher drain-efficiency mainly due to lower dissipated power in the devices.

  • 2.
    Bengtsson, Olof
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik.
    Integration and Analysis of RF-Power LDMOS Transistors2006Licentiate thesis, comprehensive summary (Other academic)
  • 3.
    Bengtsson, Olof
    et al.
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik.
    Johansson, Ted
    Nordlander, Edvard
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik.
    Rydberg, Anders
    Optimization of High-Voltage RF Power SiGe Transistors for Cellular Applications1999In: High Power Microwave Electronics: Measurements, Identification, Applications, 1999. MIA-ME '99. Proceedings of the IEEE-Russia Conference, 1999Conference paper (Refereed)
    Abstract [en]

    The base profile design for high-voltage RF power silicon transistors with epitaxial SiGe base was studied using 2-D process and device simulations. The addition of Ge in the base makes thin base widths with very high base doping possible. This gives rise to a higher maximum oscillation frequency thus improving the critical power gain for these devices

  • 4.
    Bengtsson, Olof
    et al.
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik.
    Litwin, Andrej
    Olsson, Jörgen
    Small Signal and Power Evaluation of Novel BiCMOS Compatible, Short Channel LDMOS Technology2003In: IEEE transactions on microwave theory and techniques, ISSN 0018-9480, E-ISSN 1557-9670, Vol. 51, no 3, p. 1052-1056Article in journal (Refereed)
    Abstract [en]

    We describe a very short-channel 0.15-mum LDMOS transistor with a breakdown voltage of up to 60 V, manufactured in a standard 0.35-mum BiCMOS process. At 1900 MHz and a 12-V supply voltage, the 0.4-mm-gatewidth device with shortest drain drift region gives 100-mW output power P-1 dB at a drain efficiency of 43%. It has a transducer power gain of over 20 dB. The maximum current gain cutoff frequency f(T) is 15 GHz, and the maximum available gain cutoff frequency f(MAX) is 38 GHz. We show the dependence of f(T), an f(MAX) of gate and drain bias for transistors with different-drain drift region length. The LDMOS process module does not affect the performance or the models of other devices. We present for the first time a simple way to create high-voltage high-performance LDMOS transistors for an RF power amplifier use even in a very downscaled silicon technology.

  • 5.
    Bengtsson, Olof
    et al.
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik.
    Rydberg, Anders
    Chen, Quian
    Johansson, Ted
    Ahl, Bengt
    Purroy-Martin, Fransisco
    Large-Signal Characterization and Modeling of LDMOS-Transistors for RF-Power Applications1997In: GHz97, 1997Conference paper (Other (popular science, discussion, etc.))
  • 6.
    Bengtsson, Olof
    et al.
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik.
    Vestling, Lars
    A Method for Device Intermodulation Analysis from 2D, TCAD Simulations using a Time-domain Waveform Approach2006In: Proceedings of the 36th European Microwave Conference, 2006, p. 169-171Conference paper (Refereed)
    Abstract [en]

    This paper describes a fast method useful for IMD analysis at TCAD design level. The method is based on the static load-line transfer function extracted from 2D device simulations. The transfer function is exposed to a time domain signal through a look-up table and the output response is analyzed using the Fast Fourier Transform. The response is compared to measurements of a fabricated device. The method is shown to accurately predict the IMD behavior of a two-tone signal for the 3’rd, 5’th and 7’th order IMD products with regards to sweet spot tracking and relative IMD magnitude. We present a fast and simple way to predict IMD performance from TCAD simulations at an early stage in the design process. The method enables prediction of output response from any signal due to the time domain approach.

  • 7.
    Bengtsson, Olof
    et al.
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik.
    Vestling, Lars
    FTE Uppsala Universitet.
    Olsson, Jörgen
    FTE Uppsala Universitet.
    A Computational Load-Pull Investigation of Harmonic Loading effects on AM-PM conversion2008In: GigaHertz Symposium 2008: Abstract Book, 2008, p. 83-83Conference paper (Other academic)
    Abstract [en]

    In this work computational harmonic load-pull have been used to study the effect of harmonic loading on AM-PM conversion for an RF-Power LDMOS transistor. It is found that especially the load impedance seen at the 2nd harmonic has a large impact (up to 2° or 15% difference) on the phase distortion at P1dB in this investigation conducted at chip level.

  • 8.
    Bengtsson, Olof
    et al.
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik.
    Vestling, Lars
    FTE Uppsala.
    Olsson, Jörgen
    FTE Uppsala.
    A Computational Load-Pull Method for TCAD Optimization of RF-Power Transistors in Bias-Modulation Applications2008In: 2008 European Microwave Integrated Circuits Conference (EuMIC), 2008, p. 222-225Conference paper (Refereed)
    Abstract [en]

    Abstract— In this paper a method for TCAD evaluation of RF-Power transistors for high-efficiency operation using drain bias-modulation is presented. The method is based on large signal time-domain transient computational load-pull. With the method, intrinsic device parasitics and mechanisms affecting device efficiency under drain bias modulation can be investigated and optimized for the application making it very useful for RFIC design. A case study has been done on a CMOS compatible LDMOS. For verification under dynamic operation two-tone signals with varying envelope has been simulated. The results show a possible 15% increase in the efficiency of a modulated signal for the studied device at the expense of increased phase distortion observable also in the time-domain waveforms generated. Since the method is based on TCAD it is also useful in the investigation of e.g. dynamic breakdown during high envelope under bias-modulation operation.

  • 9.
    Bengtsson, Olof
    et al.
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik.
    Vestling, Lars
    The Ångström Laboratory, Solid State Electronics, Uppsala University, Uppsala, Sweden.
    Olsson, Jörgen
    The Ångström Laboratory, Solid State Electronics, Uppsala University, Uppsala, Sweden.
    A Computational Load-Pull Method with Harmonic Loading for High-Efficiency Investigations2009In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 53, no 1, p. 86-94Article in journal (Refereed)
    Abstract [en]

    In this paper a method for TCAD evaluation of RF-power transistors in highefficiency operation using harmonic loading is presented. The method is based on large signal timedomain

    computational load-pull. Active loads are used in the harmonic load-pull for simulation time reduction. With the method device performance under different harmonic load impedance can

    be investigated at an early stage in the design process. Alternative designs can be compared and the mechanisms affecting device efficiency in class-F can be studied at chip level. For method validation a case study is made on an LDMOS transistor. The transistor is load-pulled in class-AB and then optimized for efficiency at 2f0 and 3f0 using a novel approach with passive fundamental load and active harmonic loads. A swept simulation is conducted using passive fundamental and

    harmonic loads. Waveforms in compression are analyzed and the mechanisms creating the increased efficiency for in class-F are indentified by a comparative study of class-AB. Class-F harmonic termination is shown to give a 17 % overall reduction of dissipated power and a 9 % increase in output power. The expected efficiency increase is about 3-10 % in the compression

    region depending on level of compression.

  • 10.
    Bengtsson, Olof
    et al.
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik.
    Vestling, Lars
    Solid State Electronics, Ångström Laboratory, Uppsala University, Uppsala, Sweden.
    Olsson, Jörgen
    Solid State Electronics, Ångström Laboratory, Uppsala University, Uppsala, Sweden.
    Investigation of SOI-LDMOS for RF-Power Applications Using Computational Load Pull2009In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 56, no 3, p. 505-511Article in journal (Refereed)
    Abstract [en]

    Small-signal and computational load-pull simulations are used to investigate the effect of substrate resistivity on efficiency in high-power operation of high-frequency silicon-on insulator-LDMOS transistors. Identical transistors are studied on substrates with different resistivities. Using computational load pull, their high-power performance is evaluated. The results are compared to previous investigations, relating the OFF-state out put resistance to high-efficiency operation. From the large-signal simulation, an output circuit model based on a load-line match is extracted with parameters traceable from small-signal simu lations. It is shown that, albeit high OFF-state output resistance is a good indication, it is not sufficient for high efficiency in a high-power operation. The bias and frequency dependence of the coupling through the substrate makes a more detailed ON-state analysis necessary. It is shown that very low resistivity and high resistivity SOI substrates both result in a high efficiency at the studied frequency and bias point. It is also shown that a normally doped medium-resistivity substrate results in a significantly lower efficiency.

  • 11.
    Bengtsson, Olof
    et al.
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik.
    Vestling, Lars
    The Ångström Laboratory, Solid State Electronics, Uppsala University, Uppsala, Sweden.
    Olsson, Jörgen
    The Ångström Laboratory, Solid State Electronics, Uppsala University, Uppsala, Sweden.
    Investigation of the Nonlinear Input Capacitance in LDMOS Transistors and its Contribution to IMD and Phase Distortion2008In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 52, no 7, p. 1024-1031Article in journal (Refereed)
    Abstract [en]

    In this paper the mechanisms causing the capacitive, reactive non-linearities in a lateral double diffused MOS, LDMOS, transistor are investigated. The non-linear input capacitance under load-line power match is extracted and analyzed. Computational TCAD load-pull is used to analyze the effect of non-linear capacitance on two-tone intermodulation distortion and AM–PM conversion in class-A operation. High-frequency measurements have been made to verify the use of 2D numerical device simulations for the analysis. It is found that the input capacitance, Cgg, of the LDMOS transistor working under power match conditions is a strongly non-linear function of gate voltage Vg but with an almost linear initial increase in Cgg. The voltage dependence of Cgg is found to mainly affect higher order IMD products in class-A operation. Transient simulations however show that Cgg seriously contributes to the onset of AM–PM conversion well below the 1 dB compression point.

  • 12. Castillo, Patricia
    et al.
    San-Roman, Ebert
    Bengtsson, Olof
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik.
    On the design of a planar, harmonic, triplex-filter for 3G, load-pull measurement applications2007In: RFMTC-07, 2007Conference paper (Other (popular science, discussion, etc.))
    Abstract [en]

    This paper describes the design of a planar harmonic triplex-filter for 3G load-pull measurement applications. The designs are based on planar 2D field simulations on individual and combined filters of different structures like stepped impedance, coupled lines and ring resonators. Triplex-filters of different combinations on Teflon substrate and mixed substrates for loss reduction were simulated, fabricated and evaluated in this work. It is found that using lithographic process on Teflon with SMA endlaunchers a filter with 0.44 dB f0 insertion loss, IL, and 50 dB isolation can be achieved. On the low loss substrate the mechanical design process limits the results to about 1.0 dB IL. Low loss launchers and substrate interconnects are suggested and 3D simulations performed for the mixed design.

  • 13. Litwin, Andrej
    et al.
    Bengtsson, Olof
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik.
    Olsson, Jörgen
    Novell BiCMOS Compatible, Short Channel LDMOS Technology for Medium Voltage RF & Power Applications2002In: IEEE MTT-S Digest, 2002, p. 35-38Conference paper (Refereed)
    Abstract [en]

    We describe a very short channel, 0.15 μm, LDMOS transistor, with a breakdown voltage of up to 45 V, manufactured in a standard 0.35 μm BiCMOS process. At 1900 MHz and a 12V supply voltage the 0.4mm gate width device gives 100 mW output power P1 dB at a drain efficiency of 43%. It has a transducer power gain of more than 20dB and a current gain cutoff frequency, fT, of 13 GHz. The maximum available gain cutoff frequency, fMAX, is 27 GHz. The LDMOS process module does not affect the performance or models of other devices. We present for the first time a simple way to create high voltage, high performance LDMOS transistors for RF power amplifier use even in a very downscaled silicon technology.

  • 14.
    Ramachandran , Prasadh
    et al.
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik. University of Gävle, Center for RF Measurement Technologies.
    Bengtsson , Olof
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik. University of Gävle, Center for RF Measurement Technologies.
    Beckman, Claes
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik. University of Gävle, Center for RF Measurement Technologies.
    Impedance determination of terminal power amplifiers for optimal antenna matching using load-pull method2009In: 2009 IEEE International Workshop on Antenna Technology: iWAT2009 : "Small Antennas and Novel Metamaterials", Santa Monica, California, 2009Conference paper (Refereed)
    Abstract [en]

    In this paper we present a single tuner based load-pull method for characterization of optimal antenna load impedance in mobile terminals. In the proposed load-pull set-up the mobile terminal itself is used as a source. The presented method can provide valuable data for antenna design since it determines the optimal impedance at the antenna connector/pad taken into account the full output circuitry of the mobile terminal. It reveals the modification of the power amplifier, PA, output impedance caused by the presence of saw filter, antenna switch, and transmission line possibly present between the PA and the antenna. With the presented method it is not only possible to characterize the optimum antenna impedance to present to the terminal in different bands and channels but also to reveal the impedance miss-match sensitivity for each channel.

  • 15. Vestling, Lars
    et al.
    Bengtsson, Olof
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik.
    Eklund, Klas-Håkan
    Olsson, Jörgen
    Increased efficiency in RF-power SOI-LDMOS transistors2009In: EUROSOI 2009 - Conference Proceedings: Fifth Workshop of the Thematic Network on Silicon-On-Insulator, Technology, Devices and Circuits, 2009, p. 117-118Conference paper (Refereed)
    Abstract [en]

    The effect of substrate resistivity on efficiency in high-power operation of high-frequency SOI-LDMOS transistors is for the first time investigated using computational load-pull simulations. Identical SOI-LDMOS transistors have been studied on different substrate resistivities. Their highpower performance has been compared to previous investigations concerning the off-state ROUT to high-efficiency relation. It is shown that albeit high off-state ROUT is a good indication it may not always be sufficient for high efficiency operation. The bias and frequency dependency of the coupling through the substrate makes a more detailed on-state analysis necessary. It is shown that very low resistivity and high resistivity SOI-substrates both result in high efficiency at the studied frequency and bias-point. It is also shown thata normally doped, medium resistivity, substrate results in significantly lower efficiency.

     

     

     

     

     

     

     

  • 16. Vestling, Lars
    et al.
    Bengtsson, Olof
    University of Gävle, Department of Technology and Built Environment, Ämnesavdelningen för elektronik.
    Olsson, Jörgen
    High Efficiency using Optimized SOI-Substrates2008In: Gigahertz Symposium 2008: Abstract Book, Göteborg: Chalmers , 2008, p. 94-94Conference paper (Other academic)
    Abstract [en]

    Abstract—The effect of the substrate resistivity on

    the efficiency for high-frequency SOI-LDMOS transistors

    is studied using computational load-pull simulations.

    It is shown that very low resistivity and

    high resistivity SOI-substrates both result in high

    efficiency. It is also shown that a normally doped,

    medium resistivity, substrate results in significantly

    lower efficiency.

1 - 16 of 16
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